1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a synchronous semiconductor memory device for taking in an external signal in synchronization with an externally and periodically applied clock signal. More particularly, the invention relates to a synchronous dynamic random access memory (which will be referred to as a "SDRAM" hereinafter) allowing random access.
2. Description of the Background Art
Dynamic random access memories (which will be referred to as "DRAMs") which are used as main storage units have been improved for faster operation, but the operation speeds thereof are still lower than operation speeds of microprocessors (which will be referred to as "MPUs" hereinafter). Therefore, it is often said that the access time and cycle time of the DRAM form a bottleneck in performance of a whole system. In recent years, SDRAMs which operate in synchronization with clock signals have been available as main storage units for fast MPUs.
For fast access, the SDRAM may employ such a specification that continuous bits (e.g., eight bits) per one data I/O terminal are accessed fast in synchronization with a system clock signal. FIG. 25 shows a standard timing chart satisfying this specification for continuous access. More specifically, FIG. 25 shows an operation of reading data of continuous eight bits in a SDRAM which can input and output data of 8 bits (1 byte) through data I/O terminals DQ0-DQ7. Thus, data of 64 bits (=8 bits.times.8) can be continuously read out.
The number of bits of data which are continuously read or written is called a burst length. In the SDRAM, the burst length can be changed by a mode register set.
As shown in FIG. 25, the SDRAM takes in externally supplied control signals such as a row address strobe signal /RAS, a column address strobe signal /CAS and an address signal Add, for example, at a rising edge of an externally supplied clock signal CLK which is a system clock.
Address signal Add contains a row address signal Xa and a column address signal Yb which are multiplexed together in a time sharing manner.
At the rising edge of clock signal CLK in a cycle 1, external row address strobe signal ext./RAS is active and therefore at "L" level, and external column address strobe signal ext./CAS and external write enable signal ext./WE are at "H" level. In this case, address signal Add at this point of time is taken in as a bank designating signal BA or BB and a row address signal Xa, and one row in one bank of the SDRAM memory cell array is selected in accordance with row address signal Xa.
At the falling edge of clock signal CLK in a cycle 4, external column address strobe signal ext./CAS is active and therefore at "L" level, and external row address strobe signal ext./RAS and external write enable signal ext./WE are at "H" level. When this state is attained, the operation enters a read mode, and address signal Add supplied at this point of time is taken in as bank designating signal BA or BB and a column address signal Yb. One column in the memory cell array is selected in accordance with this column address signal Yb. When a predetermined clock period (3 clock cycles in FIG. 25) elapses from the cycle in which this read mode is set, first data b0 among data of 8 bits to be output from data I/O terminal DQ is output. Thereafter, data b1-b7 are successively output in response to rising of clock signal CLK.
FIG. 26 is a timing chart showing change in external signal over time during an operation of continuously writing data of 8 bits per one data I/O terminal DQ in the SDRAM.
In the write operation, bank designating signal BA or BB and row address signal Xa are taken in similarly to the data read operation. More specifically, when such a state is achieved at the rising edge of clock signal CLK in cycle 1 that signal ext./RAS is active and therefore at "L" level, and signals ext./CAS and ext./WE are at "H" level, address signal Add at this time is taken in as bank designating signal BA or BB and row address signal Xa, and one row in one bank of the SDRAM memory cell array is selected in accordance with row address signal Xa.
When such a state is attained at the rising edge of clock signal CLK in cycle 4 that external row address strobe signal ext./RAS is at "H" level, and both signals ext./CAS and ext./WE are active and therefore at "L" level, the operation enters the write mode, and address signal Add at this time is taken in as bank designating signal BA or BB and column address signal Yb. In accordance with column address signal Yb thus taken, one column in the memory cell array is selected. At the same time, data b0 applied to data I/O terminal DQ is taken in as first write data among data of 8 bits to be continuously written, and is written into the selected memory cell.
After the cycle in which this write mode is set, input data b1-b7 are successively taken into the same row of the same bank in synchronization with clock signal CLK, and the input data is written into the memory cells designated by the column addresses which are internally and successively issued.
As described above, the SDRAM does not operate in a manner similar to that of a conventional DRAM in which the operation is performed by taking in an address signal, input data and others in synchronization with external control signals, i.e., row address strobe signal ext./RAS and column address strobe signal ext./CAS, but operates in such a manner that the external signals such as address strobe signals ext./RAS and ext./CAS, address signal and input data are taken in at the rising edge of clock signal CLK which is an externally supplied system clock.
As described above, the SDRAM performs the operation of taking in the control signals and data signals in synchronization with the externally supplied clock signal. Therefore, it is not necessary to keep a margin for a data input/output time which may be required due to a skew (shift in timing) of the address signal. This achieves an advantage that the cycle time can be reduced. Since writing and reading of continuous data can be executed in synchronization with the clock signal as described above, it is possible to reduce an access time in the operation of continuously accessing the continuous addresses.
As an architecture achieving the SDRAM, Choi et. al. has announced a SDRAM of 2-bit prefetch for writing data two bits a time (1993 Symposium on VLSI Circuit). The 2-bit prefetch operation will now be described below with reference to the drawings.
FIG. 27 shows a functional structure of a major portion of a SDRAM 300 performing the 2-bit prefetch operation in the prior art.
More specifically, FIG. 27 shows a structure of a functional portion related to input/output data of 1 bit in the SDRAM of a x16-bit structure.
The memory cell array portion related to data I/O terminal DQi includes memory cell arrays 71a and 71a' forming a bank A, and memory cell arrays 71b and 71b' forming a bank B.
Bank A is divided into memory cell array banks A0 and A1 to be selected in accordance with the address signal, and memory cell array bank B is likewise divided into memory cell array banks B0 and B1.
For memory cell array banks A0 and Al, there are provided X-decoder groups 52a and 52a' each including a plurality of row decoders for decoding address signals ext.A0-ext.Ai and selecting corresponding rows in memory cell array 71a, 71a', Y-decoder groups 53a and 53a' each including a plurality of column decoders which decode column address signals Y1-Yk and issue column select signals for selecting the corresponding columns in memory cell array 71a or 71a', and sense amplifier groups 54a and 54a' for sensing and amplifying data of the memory cells connected to the selected rows in memory cell arrays 71a and 71a', respectively.
X-decoder groups 52a and 52a' include row decoders provided correspondingly to the word lines in the memory cell arrays 71a and 71a', respectively. In accordance with internal address signals X0-Xi which are issued in response to external address signals ext.A0-ext.Ai, respectively, the corresponding row decoders selects the word lines provided correspondingly to the row decoders, respectively, and sense amplifier groups 54a and 54a' each sense the data of the selected one row.
Y-decoder groups 53a and 53a' each include column decoders provided correspondingly to column select lines in memory cell arrays 71a or 71a', respectively. The column select line selects intended data from data of one row sensed by the sense amplifier group 54a or 54a'.
X-decoder group 52a and Y-decoder group 53a select the memory cell of 1 bit in memory cell array bank A0, and X-decoder group 52a' and Y-decoder group 53a' select the memory cell of 1 bit in memory cell array bank A1. X-decoder groups 52a and 52a' as well as Y-decoder groups 53a and 53a' are activated by bank designating signal BA. For memory cell array banks B0 and B1, there are provided X-decoder groups 52b and 52b' and Y-decoder groups 53b and 53b', respectively, which are activated by bank designating signal BB.
For the bank A, there are further provided internal data transmission lines (global I/O lines) for transmitting data sensed and amplified by sense amplifier groups 54a and 54a' and for transmitting write data to the memory cells selected in memory cell arrays 71a and 71a'. More specifically, global I/O line bus GIO0 is provided for memory cell array bank A0, and global I/O line bus GIO1 is provided for memory cell array bank A1.
A write register 59a and a write buffer group 60a are provided correspondingly to global I/O line pair GIO0 for memory cell array bank A0. A write register 59a' and a write buffer group 60a' are provided correspondingly to global I/O line pair GIO1 for memory cell array bank A1.
An input buffer 58a having a width of 1 bit produces internal write data from input data sent to data I/O terminal DQi. A selector 69a is controlled by a selector control signal .phi.SEA issued from a second control signal generating circuit 63, and selectively applies an output of input buffer 58a to write registers 59a or 59a'.
Thus, input buffer 58a is activated in accordance with an input buffer activating signal .phi.WDBA, and thereby produces the internal write data from the input data applied to data I/O terminal DQi. Selector 69a is controlled in accordance with a selector control signal .phi.SEA which is issued from a second control signal generating circuit 63 in accordance with the address signal, as will be described later, and thereby sends the internal write data to one of write registers 59a and 59a'.
Write registers 59a and 59a' are activated in response to register activating signals .phi.RWA0 and .phi.RwA1, respectively, and successively store the write data sent from selector 69a. Write buffer groups 60a and 60a' are activated in response to write buffer activating signals .phi.WBA0 and .phi.WBA1, and thereby operate to amplify and transmit the data stored in corresponding write registers 59a and 59a' onto corresponding global I/O line pair buses GIO0 and GIO1, respectively.
An equalize circuit (not shown) is provided commonly for two global I/O line pairs GIO0 and GIO1. This equalize circuit is activated in response to an equalize circuit activating signal .phi.WEQA (not shown), and equalizes global I/O line pair buses GIO0 and GIO1.
Likewise, memory cell array bank B includes memory cell array banks B0 and B1. Memory cell array banks B0 and B1 include X-decoder groups 52b and 52b', Y-decoder groups 53b and 53b', sense amplifier groups 54b and 54b' which are activated in response to sense amplifier activating signal .phi.SAB, equalize circuit groups (not shown) which are activated in response to equalize circuit activating signals .phi.WEQB, write buffer groups 60b and 60b' which are activated in response to buffer activating signals .phi.WBB0 and .phi.WBB1, respectively, write registers 59b and 59b' which are activated in response to register activating signals .phi.RwB0 and .phi.RwB1, respectively, and selectors 69b and 70b which are controlled by selector control signal .phi.SEB, respectively, and also include an input buffer 58b which is activated in response to buffer activating signal .phi.WDBB.
The banks A and B have the same structures. Provision of write registers 59a and 59a' as well as 59b and 59b' allows input/output of data to and from one data I/O terminal DQ1 in synchronization with a fast clock signal.
The control signals for banks A and B are issued in accordance with bank designating signals BA and BB in such a manner that the control signals for only one of banks A and B are issued.
In the functional block for data reading, data sensed and amplified by sense amplifiers 54a and 54a' are transmitted onto buses GIO of the internal data transmitting lines (global I/O lines) provided for bank A.
For data reading, there are provided a read preamplifier 55a, which is activated in response to a preamplifier activating signal .phi.RBA0 and thereby amplifies data on global I/O line bus GIO0 in bank A0, and a read register 56a, which is activated in response to a register activating signal .phi.RrA0 and thereby stores the data amplified by read preamplifier 55a.
There are also provided a read preamplifier 55a', which is activated in response to a preamplifier activating signal .phi.RBA1 and thereby amplifies data on global I/O line bus GIO1 provided correspondingly to bank A1, and a read register 56a', which is activated in response to a register activating signal .phi.RrA1 and thereby stores the data amplified by read preamplifier 55a'.
A functional block 100 shown in FIG. 27 further includes a selector 70a which receives data from read registers 56a and 56a', and successively issues data sent from read register 56a or data sent from read register 56a' in accordance with selector signal .phi.SEA, and an output buffer 67a which receives the output of selector 70a for successively outputting the data.
Read preamplifier 55a and read register 56a each has a structure of a width of 4 bits corresponding to the four global I/O line pairs. Read register 56a is responsive to register activating signal .phi.RrA1 to latch and successively output the data sent from read preamplifier 55a.
Read preamplifier 55a' and read register 56a' operate in manners similar to those described above.
The output buffer 57a is responsive to an output enable signal .phi.OUTA to transmit the data, which is successively sent from read selector 70a, to data I/O terminal DQi. In the structure shown in FIG. 27, input and output of data are performed through data I/O terminal DQi. However, input and output of data may be performed through different terminals, respectively.
The completely same structure is employed for memory cell array bank B. Thus, the structure for memory cell array bank B includes read amplifiers B0 and B1 which are activated by read amplifier activating signals .phi.RBB0 and RBB1, respectively, read registers B0 and B1 which are activated by register activating signals .phi.RrB0 and .phi.RrB1, respectively, a selector 70b which is responsive to a signal .phi.SEB to selectively output the output of read register B0 or B1, and an output buffer 57b which is responsive to a signal .phi.OUTB to output the output data coming from selector 70b to data I/O terminal DQi.
The functional block 100 shown in FIG. 27 is arranged correspondingly to each data I/O terminal. If the SDRAM has a x16-bit structure, the SDRAM includes sixteen functional blocks 100 which correspond to the data I/O terminals, respectively.
Banks A and B have the substantially same structures and only one of them is selected in accordance with bank designating signals BA and BB, whereby the banks A and B can operate substantially independently of each other.
As a control system for independently controlling the banks A and B, there are arranged a first control signal generating circuit 62, a second control signal generating circuit 63 and a clock counter 64.
First control signal generating circuit 62 takes in the externally supplied control signals, i.e., external row address strobe signal ext./RAS, external column address strobe signal ext./CAS, chip select signal ext./CS and external write enable signal ext./WE in synchronization with external clock signal CLK, and issues internal control signals .phi.xa, .phi.ya, .phi.W, .phi.O, .phi.R and .phi.C.
Second control signal generating circuit 63 is responsive to bank designating signals BA and BB, a lowest bit Y0 of the externally applied address signal, internal control signals .phi.W, .phi.O, .phi.R and .phi.C, and the output of clock counter 64, and thereby issues control signals for independently driving banks A and B, i.e., equalize circuit activating signals .phi.WEQA and .phi.WEQB, sense amplifier activating signals .phi.SAA and .phi.SAB, write buffer activating signals .phi.WBA0, .phi.WBA1, .phi.WBB0 and .phi.WBB1, write register activating signals .phi.RwA0, .phi.RwA1, .phi.RwB0 and .phi.RwB1, selector control signals .phi.SEA and .phi.SEB, input buffer activating signals .phi.DBA and .phi.DBB, read preamplifier activating signals .phi.RBB0, .phi.RBB1, .phi.RBA0 and .phi.RBA1, read register activating signals .phi.RrB0, .phi.RrB1, .phi.RrA0 and .phi.RrA1, and output buffer activating signals .phi.OUTA and .phi.OUTB.
SDRAM 3000 further includes, as peripheral circuits, an X-address buffer 65 which is responsive to internal control signal .phi.xa and thereby operates to take in external address signals ext./A0-ext./Ai and issue internal address signals X0-Xj as well as bank select signals BA and BB, and a Y-address buffer 66 which is activated in response to internal control signal .phi.ya, and thereby issues column select signals Y0-Yk for designating the column select lines.
SDRAM 3000 further includes, as peripheral circuits, a Y-address operation circuit 68 which is controlled by clock signal CLK, and issues signals YE0-YEk and YO0-YOk which correspond to the column addresses to be selected.
Signals YE0-YEk described above represent internal column address signals corresponding to the column addresses in memory cell array bank A0 or B0, and signals YO0-YOk are internal column address signals representing the column addresses in memory cell array bank A1 or B1.
The above description has been given on the structure including only two banks. However, the banks may be generally increased in number, and the registers, buffers and I/O lines of the numbers corresponding to the number of banks may be employed. Even in this case, the banks can be accessed independently from each other.
The data is selectively written into memory cell array bank A0 or A1 in accordance with the lowest one bit of the address which is applied at the time of input of a write command.
This operation will be briefly described below. When the write command is input, the Y-decoder is activated in accordance with the applied address. The first data is stored in register A0, and then the data stored in register A0 is written into memory cell array bank A0 through I/O line GIO0 in response to activation of signal .phi.WBA0.
The data applied at the next rising edge of the clock signal is stored in register A1, and thereafter is written into memory cell array bank A1 through I/O line GIO1 in response to activation of signal .phi.WBA1. When writing of the data of 2 bits is completed, signals .phi.WBA0 and .phi.WBA1 are deactivated, and the potential levels on I/O lines GIO0 and GIO1 connecting the memory cell arrays to the buffers are equalized for next writing of data.
The 2-bit prefetch operation described above has such a disadvantage that an area penalty is large because the registers, buffers and I/O lines are required for each bank independently of the other banks. This disadvantage becomes more remarkable with increase in number of the banks and increase in number of bits of input and output.
Thus, due to a large area penalty, the 2-bit prefetch manner cannot be actually used for data reading, for example, in a so-called page mode, i.e., an operation mode that data is read from all the memory cells arranged at crossings between the selected row and all the columns crossing the selected row.
The above problem generally arises not only in the case where the stored data is read from all the memory cells present at the crossing between the selected row and all the columns crossing the selected row, but also in the case where the stored data is simultaneously read from a large number of memory cells among those present at the crossing between the selected row and the columns crossing the selected row.
For the above problem, Takai et. al. has announced a SDRAM of a pipeline type (1993 Symposium on VLSI Circuit). FIG. 28 shows a structure of this SDRAM 4000. FIG. 28 schematically shows a structure of a functional portion 300 of SDRAM 4000.
A difference with respect to SDRAM 3000 in FIG. 27 is as follows. In SDRAM 3000, each of memory cell array banks A and B is further divided into banks A0 and A1 or banks B0 and B1. However, SDRAM 4000 does not employ this structure. Therefore, the numbers of required registers, buffers and I/O lines are equal to those of a standard DRAM, and a difference with respect to the standard DRAM is that a latch circuit is arranged on a critical path of data transmission.
In contrast to SDRAM 3000, the registers, buffers and I/O lines are not distinguished for banks A0 and A1, and are commonly used for both the banks.
The data to be continuously written can be processed in such a manner that input data is written into the register while preceding data latched by the register is being written into the corresponding memory cell array bank. However, this data writing is performed bit by bit in contrast to the 2-bit prefetch type. Therefore, an operation frequency cannot be increased compared with the 2-bit prefetch type allowing simultaneous writing of data of two bits.